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ARA2001
Reverse Amplifier with Step Attenuator
FEATURES
* * * * * * * * * * * *
Data Sheet - Rev 2.2
Low cost integrated amplifier with step attenuator Attenuation Range: 0-58 dB, adjustable in 1dB increments via a 3 wire serial control Meets DOCSIS distortion requirements at +60dBmV output signal level Low distortion and low noise Frequency range: 5-100MHz 5 Volt operation -40 to +85 0C temperature range MCNS/DOCSIS Compliant Cable Modems CATV Interactive Set-Top Box Telephony over Cable Systems OpenCable Set-Top Box Residential Gateway
APPLICATIONS
S23 Package 28 Pin SSOP with Exposed Paddle
performance at a +60dBmV output level while only requiring a single polarity +5V supply. Both the input and output are matched to 75 ohms with an appropriate transformer. The precision attenuator provides up to 58 dB of attenuation in 1 dB increments. The ARA2001 is offered in a 28-pin SSOP package featuring an exposed paddle on the bottom of the package.
PRODUCT DESCRIPTION
The ARA2001 is designed to provide the reverse path amplification and output level control functions in a CATV Set-Top Box or Cable Modem. It incorporates a digitally controlled precision step attenuator that is preceded by an ultra low noise amplifier stage, and followed by an ultra-linear output driver amplifier. This device uses a balanced circuit design that exceeds the MCNS/DOCSIS requirement for harmonic
Clock Data Enable
Balun
ARA2001
Low Pass Filter
Upstream QPSK/16QAM Modulator
Clock Data
RAM
ROM
5-42 MHz
Transmit Enable/Disable
MAC
Clock 44 MHz Data
Microcontroller with Ethernet MAC
Diplexer
54-860 MHz
DoubleConversion Tuner
SAW Filter
QAM Receiver with FEC
10Base-T Transceiver
RJ45 Connector
Figure 1. Cable Modem or Set Top Box Application Diagram
07-2001
ARA2001
GaAs IC
ATTIN (+) A1OUT (+) A1IN (+)
32 dB 16 dB 8 dB 4 dB 2 dB 1 dB
ATTOUT (+) A2IN (+) A2OUT (+) ISET2
EFET
ISET1 Vg1 A1IN (-) A1OUT (-) ATTIN (-)
EFET
Vg2 A2OUT (-) A2IN (-) ATTOUT (-)
32 dB P5
16 dB P4
8 dB P3
4 dB P2
2 dB P1
1 dB P0
Buffer
Clock
Data
8-Bit Shift Register/ Address
8
Control Latch
Enable
CMOS IC (Serial to Parallel Interface)
Figure 2: Functional Block Diagram
1 2 3 4 5 6 7 8 9 10 11 12 13 14
GND VATTN ATTIN (+) A1OUT (+) A1IN (+) Vg1 ISET1 A1IN (-) A1OUT (-) ATTIN (-) VCMOS CLK DAT EN
GND N/C ATTOUT (+) A2IN (+) A2OUT (+) Vg2 ISET2 A2OUT (-) A2IN (-) ATTOUT (-) GNDCMOS N/C N/C N/C
28 27 26 25 24 23 22 21 20 19 18 17 16 15
Figure 3: Pin Out 2
Data Sheet - Rev 2.2 07-2001
ARA2001
Table 1: Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 N AME GND VATTN ATTIN (+) A1OUT (+) A1IN (+) V g1 ISET1 A1IN (-) A1OUT (-) ATTIN (-) VCMOS C LK D AT EN D ESC R IPTION Ground Supply for Attenuator Attenuator (+) Input (2) Ampli fi er A1 (+) Output Ampli fi er A1 (+) Input (2) Ampli fi er A1 (+/-) C ontrol Ampli fi er A1 (+/-) C urrent Adjust Ampli fi er A1 (-) Input (2) Ampli fi er A1 (-) Output Attenuator (-) Input (2) Supply For D i gi tal C MOS C i rcui t C lock D ata Enable PIN 15 16 17 18 19 20 21 22 23 24 25 26 27 28 N AME N/C N/C N/C GND CMOS ATTOUT (-) A2IN (-) A2OUT (-) ISET2 V g2 A2
OUT
D ESC R IPTION No C onnecti on (1) No C onnecti on (1) No C onnecti on (1) Ground for D i gi tal C MOS C i rcui t Attenuator (-) Output (2) Ampli fi er A2 (-) Input (2) Ampli fi er A2 (-) Output Ampli fi er A2 (+/-) C urrent Adjust Ampli fi er A2 (+/-) C ontrol Ampli fi er A2 (+) Output Ampli fi er A2 (+) Input (2) Attenuator (+) Output (2) No C onnecti on (1) Ground
(+)
A2 IN (+) ATTOUT (+) N/C GND
Notes: (1) All N/C pins should be grounded. (2) Pins should be AC-coupled. No external DC bias should be applied.
Data Sheet - Rev 2 07-2001
3
ARA2001
ELECTRICAL CHARACTERISTICS
Table 2: Absolute Minimum and Maximum Ratings
PAR AMETER Analog Supply (pi ns 2, 4, 9, 21, 24) D i gi tal Supply: VCMOS (pi n 11) Ampli fi er C ontrols Vg1, Vg2 (pi ns 6, 23)
RF Power at Inputs (pi ns 5, 8)
MIN 0 0 -5 -0.5 -55 -
MAX 9 6 2 +60 VCMOS+0.5 +200 260 5
U N IT VD C VD C V dBmV V
0
D i gi tal Interface (pi ns 12, 13, 14) Storage Temperature Solderi ng Temperature Solderi ng Ti me
C C
0
S ec
Stresses in excess of the absolute ratings may cause permanent damage. Functional operation is not implied under these conditions. Exposure to absolute ratings for extended periods of time may adversely affect reliability. Notes: 1. Pins 3, 5, 8, 10, 19, 20, 25 and 26 should be AC-coupled. No external DC bias should be applied. 2. Pins 7 and 22 should be grounded or pulled to ground through a resistor. No external DC bias should be applied.
Table 3: Operating Ranges
PAR AMETER Ampli fi er Supply: VDD (pi ns 4, 9, 21, 24) Attenuator Supply: VATTN (pi n 2) D i gi tal Supply: VCMOS (pi n 11) D i gi tal Interface (pi ns 12, 13, 14) Ampli fi er C ontrols Vg1, Vg2 (pi ns 6, 23) C ase Temperature
MIN 4.5 VDD-0.5 3.0 0 -5 -40
TYP 5 5 1 25
MAX 7 7 5.5 VCMOS 2 85
U N IT VD C VD C VD C V V
0
C
The device may be operated safely over these conditions; however, parametric performance is guaranteed only over the conditions defined in the electrical specifications.
4
Data Sheet - Rev 2.2 07-2001
ARA2001 Table 4: DC Electrical Specifications TA=25C; VDD, VATTN, VCMOS = +5.0 VDC; Vg1, Vg2 = +1.0 V (Tx enabled); Vg1, Vg2 = 0 V (Tx disabled)
PAR AMETER Ampli fi er A1 C urrent (pi ns 4, 9) Ampli fi er A2 C urrent (pi ns 21, 24) Attenuator C urrent (pi n 2) Total Power C onsumpti on
MIN -
TYP 48 2.4 77 3.7 9 0.67 75
MAX 80 6 120 9 15 1.08 150
U N IT mA mA mA W mW
C OMMEN TS Tx enabled Tx di sabled Tx enabled Tx di sabled
Tx enabled Tx di sabled
Table 5: AC Electrical Specifications TA=25C; VDD, VATTN, VCMOS = +5.0 VDC; Vg1, Vg2 = +1.0 V (Tx enabled); Vg1, Vg2 = 0 V (Tx disabled)
PAR AMETER Gai n (10 MHz) Gai n Flatness Gai n Vari ati on over Temperature Attenuati on Steps 1 dB 2 dB 4 dB 8 dB 16 dB 32 dB MIN 27.5 0.65 1.6 3.6 7.5 15.0 30.2 58.6 78 TYP 29.3 0.75 1.5 -0.006 0.83 1.70 3.75 7.75 15.40 30.75 60.3 -75 -60 68.5 3.0 MAX 30.5 1.00 2.05 4.0 8.0 15.8 31.3 -53 -53 4.0 U N IT dB dB dB/C C OMMEN TS 0 dB attenuati on setti ng 5 to 42 MHz 5 to 65 MHz
dB
Monotoni c
Maxi mum Attenuati on 2nd Harmoni c D i storti on Level (10 MHz) 3rd Harmoni c D i storti on Level (10 MHz) 3rd Order Output Intercept 1 dB Gai n C ompressi on Poi nt Noi se Fi gure
Note: As measured in ANADIGICS test fixture
dB dB c dB c dBmV dBmV dB Includes i nput balun loss +60 dBmV i nto 75 Ohms +60 dBmV i nto 75 Ohms
Data Sheet - Rev 2 07-2001
5
ARA2001
continued: AC Electrical Specifications TA=25C; VDD, VATTN, VCMOS = +5.0 VDC; Vg1, Vg2 = +1.0 V (Tx enabled); Vg1, Vg2 = 0 V (Tx disabled)
PAR AMETER Output Noi se Power Acti ve / No Si gnal / Mi n. Atten. Set. Acti ve / No Si gnal / Max. Atten. Set. Isolati on (45 MHz) i n Tx di sable mode
MIN -
TYP 65
MAX -38.5 -53.8 -
U N IT dBmV
C OMMEN TS Any 160 kHz bandwi dth from 5 to 42 MHz D i fference i n output si gnal between Tx enable and Tx di sable between pi ns 5 and 8 (Tx enabled) wi th transformer (Tx enabled) Tx enabled Tx di sabled between pi ns 21 and 24 wi th transformer Tx enabled Tx di sabled 0 dB attenuator setti ng 24 dB attenuator setti ng
dB
D i fferenti al Input Impedance Input Impedance Input Return Loss (75 Ohm characteri sti c i mpedance) D i fferenti al Output Impedance Output Impedance Output Return Loss (75 Ohm characteri sti c i mpedance) Output Voltage Transi ent Tx enable / Tx di sable
Note: As measured in ANADIGICS test fixture
-
300 75 -20 -5 300 75 -17 -15 4
-12 -12 -10 100 7
Ohms Ohms dB Ohms Ohms dB mVp-p
6
Data Sheet - Rev 2.2 07-2001
Control A1 0 / +3 V
+5 V
Control A2 0 / +3 V
+5 V
1uF 2K Ohms 1K Ohms 0.1uF 2K Ohms 10uH 470pF 1000pF 1.2K Ohms 1000pF
2 3 1
2K Ohms 1K Ohms
1uF
GND VATTN ATTIN (+) A1OUT (+) A1IN (+) Vg1 ISET1 A1IN (-) A1OUT (-) ATTIN (-) VCMOS CLK DAT EN ARA2001
GND ATTOUT (+) A2IN (+) A2OUT (+)
28
0.1uF
26 25 24 23
N/C 27
2K Ohms 470pF 470pF Turns Ratio 2:1 RF Output (75 Ohms)
Figure 4: Test Circuit
RF Input (75 Ohms)
Turns Ratio 1:2
Data
+5 V
+5 V
Enable
Clock
Data Sheet - Rev 2 07-2001
4 5 6 7
1500pF
3.9 Ohms 1.2K Ohms 1000pF 1000pF 10uH 1uF 1uF
Vg2 ISET2 22 A2OUT (-) 21 A2IN (-) ATTOUT (-) GNDCMOS N/C
20 19 18 17
8 9 10 11 12 13 14
Toko Balun 616PT-1030 470pF
N/C 16 N/C
15
0.1uF
0.1uF
Note: Tx Enable: Control A1 and Control A2 = +3V Tx Disable: Control A1 and Control A2 = 0V
ARA2001
7
ARA2001
PERFORMANCE DATA
Figure 5: Attenuation Level vs Control Word
64 60 56 52 48 44 40 36 32 28 24 20 16 12 8 4 0 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 Control Word
Attenuation (dB)
Figure 6: Gain & Noise Figure vs Frequency
Gain 35 30 25 Gain (dB) 20 15 10 5 10 30 50 Frequency (MHz) 70 90 Noise Figure 8 7 6 5 4 3 2 NF (dB)
6 5 3 2 Measured @ 30 MHz 20 3 4 5 VDD ( Volts ) 6 7 1 NF (dB) 4
Figure 7: Gain & Noise Figure vs VDD
35 Gain Noise Figure
32 GAIN (dB)
29
26
23
8
Data Sheet - Rev 2.2 07-2001
ARA2001
Figure 8: Gain & Noise Figure vs Temperature
35 Gain Noise Figure 6
32 GAIN (dB)
5
26
3
23 Measured @ 30 MHz 20 -40 -25 -10 5 20 35
o
2
1 50 65 80
Temperature (C )
Figure 9: Harmonic Distortion vs VDD
POUT = 58dBmV
2nd Harmonic -20 -30 Harmonic Level (dBc) -40 -50 -60 -70 Measured @ 5 MHz -80 3 4 5 VDD ( Volts ) 6 7 3rd Harmonic
Figure 10: Harmonic Distortion vs VDD
POUT = 58dBmV
2nd Harmonic -20 -30 Harmonic Level (dBc) -40 -50 -60 -70 Measured @ 12 MHz -80 3 4 5 VDD ( Volts ) 6 7 3rd Harmonic
NF (dB)
29
4
Data Sheet - Rev 2 07-2001
9
ARA2001 Figure 11: Harmonic Distortion vs Temperature
POUT = 58dBmV
2nd Harmonic -40 -45 Harmonic level (dBc) -50 -55 -60 -65 -70 -75 -80 -40 -25 -10 5 20 Measured @ 5 MHz 35 50 65 80 3rd Harmonic
Temperature (Co)
Figure 12: Harmonic Distortion vs Power Out
2nd -30 -35 -40 Harmonics (dBc) -45 -50 -55 -60 -65 -70 -75
49 51 53 55 57 59 61 63 65 67
3rd
Pout (dBmV)
Figure 13: Transients vs Attenuation
POUT = 55dBmV at 0dB attenuation
DOCSIS 1.1 Spec. 100 90 80 Transient (mV) 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 Power Attenuation (dB)
ARA2001 ARA2001
10
Data Sheet - Rev 2.2 07-2001
ARA2001 Figure 14: Harmonic Performance over Frequency POUT = +62dBmV
2nd Harmonic -50 -52 Harmonic Level (dBc) -54 -56 -58 -60 -62 -64 -66 -68 -70 -72 0 5 10 15 20 Frequency (MHz) 25 30 35 40 3rd Harmonic
Figure 15: IIP2 & IIP3 vs Frequency
IIP2 40 IIP3 14
36 IIP2 (dBm)
12 IIP3 (dBm)
IIP3 (dBm)
32
10
28
8
24 Measured @ V DD = 5 Volts Pin = -20 dBm per tone 20 5 15 25 35 45 55 65 Frequency (MHz) 75 85 95
6
4
Figure 16: IIP2 & IIP3 vs VDD
IIP2 40 IIP3 15
36
11
IIP2 (dBm)
32
7
28
3
24 Measured @ 65 MHz Two tones @ 29.5 MHz 20 3 4 5 VDD (Volts) 6 7
-1
-5
Data Sheet - Rev 2 07-2001
11
ARA2001
LOGIC PROGRAMMING
Programming Instructions The programming word is set through an 8 bit shift register via the data, clock and enable lines. The data is entered in order with the most significant bit (MSB) first and the least significant bit (LSB) last.
The enable line must be low for the duration of the data entry, then set high to latch the shift register. The rising edge of the clock pulse shifts each data value into the register.
Table 6: Programming Word
D ATA B IT Value D7 P7 D6 P6 D5 P5 D4 P4 D3 P3 D2 P2 D1 P1 D0 P0
Table 7: Data Description
V AL U E P7 P6 P5 P4 P3 P2 P1 P0 FU N C TION (1 = on, 0 = by pass) N/A N/A 32 dB Attenuator Bi t 16 dB Attenuator Bi t 8 dB Attenuator Bi t 4 dB Attenuator Bi t 2 dB Attenuator Bi t 1 dB Attenuator Bi t
DATA
D7: MSB
D6
D4
D3
D1
D0: LSB
CLOCK
ENABLE OR ENABLE
Figure 17: Serial Data Input Timing 12
Data Sheet - Rev 2.2 07-2001
ARA2001
APPLICATION INFORMATION
Transmit Enable / Disable The ARA2001 includes two amplification stages that each can be shut down through external control pins Vg1 and Vg2 (pins 6 and 23, respectively.) By applying a slightly positive bias of typically +1.0 Volts, the amplifier is enabled. In order to disable the amplifier, the control pin needs to be pulled to ground. A practical way to implement the necessary control is to use bias resistor networks similar to those shown in the test circuit schematic (Figure 4.) Each network includes a resistor shunted to ground that serves as a pull-down to disable the amplifier when no control voltage is applied. When a positive voltage is applied, the network acts as a voltage divider that presents the required +1.0 Volts to enable the amplifier. By selecting different resistor values for the voltage divider, the network can accommodate different control voltage inputs. The Vg1 and Vg2 pins may be connected together directly, and controlled through a single resistor network from a common control voltage. Amplifier Bias Current The ISET pins (7 and 22) set the bias current for the amplification stages. Grounding these pins results in the maximum possible current. By placing a resistor from the pin to ground, the current can be reduced. The recommended bias conditions use the configuration shown in the test circuit schematic in Figure 4. Thermal Layout Considerations The device package for the ARA2001 features an exposed paddle on the bottom of the package body. Use of the paddle is an integral part of the device design. Soldering this paddle to the ground plane of the PC board will ensure the lowest possible thermal resistance for the device, and will result in the longest MTF (mean time to failure.) A PC board layout that optimizes the benefits of the paddle is shown in Figure 18. The via holes located under the body of the device must be plated through to a ground plane layer of metal, in order to provide a sufficient heat sink. The recommended solder mask outline is shown in Figure 19.
Figure 18: PC Board Layout
Data Sheet - Rev 2 07-2001
13
ARA2001 Output Transformer Matching the output of the ARA2001 to a 75 Ohm load is accomplished using a 2:1 turns ratio transformer. In addition to providing an impedance transformation, this transformer provides the bias to the output amplifier stage via the center tap. The transformer also cancels even mode distortion products and common mode signals, such as the voltage transients that occur while enabling and disabling the amplifiers. As a result, care must be taken when selecting the transformer to be used at the output. It must be capable of handling the RF and DC power requirements without saturating the core, and it must have adequate isolation and good phase and amplitude balance. It also must operate over the desired frequency and temperature range for the intended application. ESD Sensitivity Electrostatic discharges can cause permanent damage to this device. Electrostatic charges accumulate on test equipment and the human body, and can discharge without detection. Proper precautions and handling are strongly recommended. Refer to the ANADIGICS application note on ESD precautions.
Figure 19: Solder Mask Outline
14
Data Sheet - Rev 2.2 07-2001
ARA2001
PACKAGE OUTLINE
SYMBOLS
DIMENSIONS IN INCHES
DIMENSIONS IN MILLIMETERS
A A1 A2 b C D E H e L y T S
MIN 0.057 0.000 0.057 0.008 0.007 0.386 0.150 0.228 0.025 0.016 --- 0 --- ---
MAX 0.061 0.004 0.012 0.010 0.394 0.157 0.244 0.050 0.004 8 0.190 0.096
MIN 1.45 0.00 0.20 0.18 9.80 3.81 5.80 0.40 --- 0 --- ---
1.45
MAX 1.55 0.10 0.30 0.25 10.00 4.00 6.20 1.27 0.10 8 4.82 2.43
NOTE 1. PACKAGE BODY SIZES EXCLUDE MOLD FLASH AND GATE BURRS 2. TOLERANCE 0.004in.[0.10 mm] UNLESS OTHERWISE SPECIFIED 3. CONTROLLING DIMENSION ARE INCHES. 4. REF. - MO-137
.64
Figure 20: S23 Package Outline - 28 Pin SSOP with Exposed Paddle
Data Sheet - Rev 2 07-2001
15
ARA2001
COMPONENT PACKAGING
Volume quantities of the ARA2001 are supplied on tape and reel. Each reel holds 3,500 pieces. Smaller quantities are available in plastic tubes of 50 pieces.
Figure 21: Reel Dimensions
DIRECTION OF FEED
Figure 22: Tape Dimensions 16
Data Sheet - Rev 2.2 07-2001
ARA2001
NOTES
Data Sheet - Rev 2 07-2001
17
ARA2001
NOTES
18
Data Sheet - Rev 2.2 07-2001
ARA2001
NOTES
Data Sheet - Rev 2 07-2001
19
ARA2001
ORDERING INFORMATION
OR D ER N U MB ER ARA2001S23TR ARA2001S23P0 TEMPER ATU R E R AN GE -40 to 85 0C -40 to 85 0C PAC K AGE D ESC R IPTION 28 Pi n SSOP wi th Exposed Paddle 28 Pi n SSOP wi th Exposed Paddle C OMPON EN T PAC K AGIN G 3,500 pi ece tape and reel Plasti c tubes (50 pi eces per tube)
ANADIGICS, Inc.
141 Mount Bethel Road Warren, New Jersey 07059, U.S.A. Tel: +1 (908) 668-5000 Fax: +1 (908) 668-5132 URL: http://www.anadigics.com E-mail: Mktg@anadigics.com IMPORTANT NOTICE
ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without notice. The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are subject to change prior to a products formal introduction. Information in Data Sheets have been carefully checked and are assumed to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges customers to verify that the information they are using is current before placing orders.
ANADIGICS products are not intended for use in life support appliances, devices or systems. Use of an ANADIGICS product in any such application without written consent is prohibited.
WARNING
20
Data Sheet - Rev 2.2 07-2001

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